Design considerations of a nonvolatile accumulator-based 8-bit processor

The rise of the Internet of Things (IoT) and theconstant growth of portable electronics have leveraged the con-cern with energy consumption. Nonvolatile memory (NVM)emerged as a solution to mitigate the problem due to its abilityto retain data on sleep mode without a power supply. Non-volatile processors (NVPs) may further improve energy savingby using nonvolatile flip-flops (NVFFs) to store system state,allowing the device to be turned off when idle and resume ex-ecution instantly after power-on. In view of the potential pre-sented by NVPs, this work describes the initial steps to imple-ment a nonvolatile version of Neander, a hypothetical processorcreated for educational purposes. First, we implemented Ne-ander in Register Transfer Level (RTL), separating the com-binational logic from the sequential elements. Then, the lat-ter was replaced by circuit-level descriptions of volatile flip-flops. We then validated this implementation by employinga mixed-signal simulation over a set of benchmarks. Resultshave shown the expected behavior for the whole instructionset. Then, we implemented circuit-level descriptions of mag-netic tunnel junction (MTJ) based nonvolatile flip-flops, usingan open-source MTJ model. These elements were exhaustivelyvalidated using electrical simulations. With these results, weintend to carry on the implementation and fully equip our pro-cessor with nonvolatile features such as instant wake-up

On the design of hybrid CMOS and magnetic memories, with applications to reconfigurable architectures.

Avec la réduction continue des dimensions des transistors CMOS, le développement des mémoires statiques du type SRAM énergétiquement efficientes et de hautes densités devient de plus en plus difficile. Les dernières années ont vu l'apparition de nouvelles technologies de mémoire, qui ont attiré l'intérêt de la communauté académique, ainsi que de nombreux acteurs industriels. Parmi ces technologies, la STT-MRAM se distingue pour ses caractéristiques très avantageuses, comme sa faible consommation, ses performances et sa facilité d'intégration dans une technologie de fabrication CMOS. En plus, les MRAMs sont des technologies non-volatiles, avec une endurance élevée, nous allons utiliser cette caractéristique pour proposer de nouvelles fonctionnalités aux systèmes intégrés, notamment sur les architectures de processeur et les dispositifs reconfigurables.Une comparaison entre plusieurs amplificateurs de lecture, utilisables pour concevoir des matrices de mémoire et des cellules séquentielles a été aussi menée. Afin de démontrer la faisabilité de la conception hybride CMOS/MRAM plusieurs prototypes ont été conçus sur une technologie 28nm CMOS FDSOI et une technologie magnétique capable de produire des MTJ perpendiculaires STT de 200nm. Nous avons appliqué ces briques de base au monde du processeur notamment en proposant un processeur capable de conserver un état sain lors d'une erreur d'exécution. Les résultats obtenus confirment que le surcout de ces techniques est tout à fait compatible avec la démarche de conception d'un circuit intégré actuel.With the downscaling of the CMOS technology, it is becoming increasingly difficult to design power-efficient and dense static random-access memories (SRAM). In the last two decades, alternative memory technologies have been actively researched both by academia and industry. Among them, STT-MRAM is one of the most promising, having near-zero static power consumption, competitive performance with respect to SRAM and easy integration with CMOS fabrication processes. Furthermore, MRAM is a non-volatile memory technology, providing for new features and capabilities when embedded in reconfigurable devices or processors. In this thesis, applications of MRAM to embedded processors and field-programmable gate-arrays (FPGAs) were investigated. A comparison of several self-referenced read circuits, with application for both memory arrays and sequential cells is provided, based on MTJ compact models provided by our project partners. To demonstrate the feasibility of the proposed circuits, we laid-out and fabricated independent, self-contained sequential cells and a hybrid, multi-context CMOS/MTJ memory array, using state-of-the-art 28nm FDSOI CMOS technology, combined with a 200nm perpendicular STT-MTJ process. Finally, we used these building blocks to implement instant on/off and backward-error recovery capabilities in an embedded processor. Results obtained by simulation allowed us to verify that these features have minimal impact on performance. An initial layout implementation allowed us to estimate the impact on silicon footprint, which could be further reduced by improvements in the MTJ integration process

Evaluation of hybrid MRAM/CMOS cells for “normally-off and instant-on” computing

International audienceTo meet the ever-growing demand for higher computing throughput, the clock frequency of the processor was continually increased. After decades of success, this trend stopped at frequencies of 2–3 GHz due to heating issues and energy consumption. To keep pace, multi-core processor architectures began to rise. This, in turn, significantly increased the amount of the SRAM-based cache memory required. As a result, cache memory now occupies large proportion of recent processor chips. In addition, it has become a major source of the leakage power consumption. The power gating technique applied on a SRAM cache is not efficient since it is paid by data loss and by the significant time and the energy required to retrieve the lost data. In this paper, we present three memory cells that can overcome this issue. They combine a conventional volatile CMOS part with magnetic tunnel junctions (MTJs) able to store a data bit in a non-volatile way. Being inherently non-volatile, these hybrid cells enable instantaneous power off and thus complete reduction of the leakage power. Moreover, given that the data bit can be stored in local MTJs and not in distant storage memories, these cells also offer instantaneous and efficient data retrieval. To demonstrate their functionality, the cells are designed using 28 nm FD-SOI technology for the CMOS part and 45 nm round spin transfer torque MTJs (STT-MTJs) with perpendicular magnetization anisotropy. We report the measured performances of the cells in terms of required silicon area, robustness, read/write speed and energy consumption. We also demonstrate that the body-biasing technique offered by the FD-SOI technology can be used to boost the performances of the hybrid cells

A hybrid magnetic/complementary metal oxide semiconductor three-context memory bit cell for non-volatile circuit design

International audienceAter decades of continued scaling to the beat of Moore's law, it now appears that conventional silicon based devices are approaching their physical limits. In today's deep-submicron nodes, a number of short-channel and quantum effects are emerging that affect the manufacturing process, as well as, the functionality of the microelectronic systems-on-chip. Spintronics devices that exploit both the intrinsic spin of the electron and its associated magnetic moment, in addition to its fundamental electronic charge, are promising solutions to circumvent these scaling threats. Being compatible with the CMOS technology, such devices offer a promising synergy of radiation immunity, infinite endurance, non-volatility, increased density, etc. In this paper, we present a hybrid (magnetic/CMOS) cell that is able to store and process data both electrically and magnetically. The cell is based on perpendicular spin-transfer torque magnetic tunnel junctions (STT-MTJs) and is suitable for use in magnetic random access memories and reprogrammable computing (non-volatile registers, processor cache memories, magnetic field-programmable gate arrays, etc). To demonstrate the potential our hybrid cell, we physically implemented a small hybrid memory block using 45 nm × 45 nm round MTJs for the magnetic part and 28 nm fully depleted silicon on insulator (FD-SOI) technology for the CMOS part. We also report the cells measured performances in terms of area, robustness, read/write speed and energy consumption

Embedded Memory Hierarchy Exploration Based on Magnetic Random Access Memory

International audienceStatic random access memory (SRAM) is the most commonly employed semiconductor in the design of on-chip processor memory. However, it is unlikely that the SRAM technology will have a cell size that will continue to scale below 45 nm, due to the leakage current that is caused by the quantum tunneling effect. Magnetic random access memory (MRAM) is a candidate technology to replace SRAM, assuming appropriate dimensioning given an operating threshold voltage. The write current of spin transfer torque (STT)-MRAM is a known limitation; however, this has been recently mitigated by leveraging perpendicular magnetic tunneling junctions. In this article, we present a comprehensive comparison of spin transfer torque-MRAM (STT-MRAM) and SRAM cache set banks. The non-volatility of STT-MRAM allows the definition of new instant on/off policies and leakage current optimizations. Through our experiments, we demonstrate that STT-MRAM is a candidate for the memory hierarchy of embedded systems, due to the higher densities and reduced leakage of MRAM.We demonstrate that adopting STT-MRAM in L1 and L2 caches mitigates the impact of higher write latencies and increased current draw due to the use of MRAM. With the correct system-on-chip (SoC) design, we believe that STT-MRAM is a viable alternative to SRAM, which minimizes leakage current and the total power consumed by the SoC

Spintronic Memory-Based Reconfigurable Computing

International audienceReconfigurable computing provides a number of advantages such as low Research and Development (R&D) cost and design flexibility when compared to application specific logic circuits (ASLC). However its low power efficiency greatly limits its applications. One of the major reasons of this shortcoming is that Static Random Access Memory (SRAM)-based configuration memory occupies a large die area and consumes high static power. The later is more severe due to the rapidly increasing leakage currents, which are intrinsic and become worse following the fabrication node shrinking. Spintronic memories (e.g., STT-MRAM and racetrack memory (RM)) are emerging nonvolatile memory technologies under intense investigation by both academics and industries. They promise ultra-high storage density, nonvolatility and low power. In this paper, we review the current status of spintronic memories for reconfigurable computing, the related device-circuit-system design requirements and present its perspectives. Mixed simulations based on spintronic device compact models show its high density and low power performance when compared to conventional SRAM-based reconfigurable computing

High Performance SoC Design Using Magnetic Logic and Memory

International audienceAs the technolody node shrinks down to 90nm and below, high standby power becomes one of the major critical issues for CMOS highspeed computing circuits (e.g. logic and cache memory) due to the high leakage currents. A number of non-volatile storage technologies, such as FRAM, MRAM, PCRAM and RRAM, are under investigation to bring the non-volatility into the logic circuits and then eliminate completely the standby power issue. Thanks to its infinite endurance, high switching/sensing speed and easy integration on top of CMOS process, MRAM is considered as the most promising one. Numerous logic circuits based on MRAM technology have been proposed and prototyped in the last years. In this paper, we present an overview and current status of these logic circuits and discuss their potential applications in the future from both physical and architectural points of view